module bin_bcd (input en,
                input clk,
                input rst_n,
                input [7:0] bin,
                output [3:0] hund,ten,bits
				);
    
    reg [19:0] tran_shift; 	//8+12 = 20 定义转换缓存
    wire [19:0] next_tran_shift;
	reg [12:0] get_tran;
    reg [3:0] count;		//计数器
    
    always @(posedge clk or negedge rst_n) begin
        if (rst_n == 1'b0) begin
            count <= 4'd0;
        end
        else begin
            if (count == 4'd8) begin
                count <= 4'd0;
            end
            else begin
                count <= count + 1'b1;
            end
        end
    end
    
	always @(posedge clk or negedge rst_n) begin
		if (rst_n == 1'b0) begin
			tran_shift <= 20'd0;
			get_tran <= 12'd0;
		end
		else begin
			if (count == 4'd0) begin
				get_tran <= tran_shift[19:8];
				tran_shift <= {12'd0,bin};
			end
			else begin
				tran_shift <= next_tran_shift << 1;
			end
		end
		
	end

	assign next_tran_shift[19:16] = (tran_shift[19:16] >= 4'd5)? (tran_shift[19:16] + 4'd3):tran_shift[19:16];
	assign next_tran_shift[15:12] = (tran_shift[15:12] >= 4'd5)? (tran_shift[15:12] + 4'd3):tran_shift[15:12];
	assign next_tran_shift[11:8] = (tran_shift[11:8] >= 4'd5)? (tran_shift[11:8] + 4'd3):tran_shift[11:8];
	assign next_tran_shift[7:0] = tran_shift[7:0];
    
	assign hund = get_tran[11:8];
	assign ten  = get_tran[7:4];
	assign bits = get_tran[3:0];

endmodule
